Amplifiers are commonly used in various electronic devices to provide signal amplification. For example, a receiver in a wireless communications system may include a low noise amplifier (LNA) to amplify a low-amplitude signal received via a communication channel. The LNA is often the first active circuit encountered by the received signal and hence may significantly impact the performance of the receiver. Accordingly, nonlinearities may impact the design of (and often place more stringent requirements on) subsequent stages in order to meet the overall performance requirements for the receiver. Thus, among other advantages, having a more linear LNA can alleviate the performance requirements for other stages, which may result in lower power consumption and smaller circuit area for the receiver.
The linearity of a receiver (or the active devices therein) can be characterized by the input-referred third-order intercept point (IIP3). Typically, an output radio frequency (RF) signal and third-order intermodulation products are plotted versus the input RF signal. As the input RF signal is increased, the IIP3 is a theoretical point where the desired output RF signal and the third-order products become equal in amplitude. The IIP3 is an extrapolated value since the active device goes into compression before the IIP3 point is reached.
Various circuits have been devised to improve the IIP3 of common amplifiers, such as LNAs. For example, a modified derivative superposition (MDS) scheme has been shown to work well in silicon, achieving an IIP3 greater than +10 dBm. MDS is described in more detail, for example, in Vladimir Aparin and Lawrence E. Larson, “Modified Derivative Superposition method for Linearizing FETs for Low-Noise Amplifiers,” IEEE Trans. On Microwave Theory and Techniques, Vol. 52, No. 3, February 2005, pp. 571-581. However, one of the limitations of this scheme is its narrow-band frequency operating region, making it undesirable for wideband applications, such as TV tuners, ultra wide band systems, etc. In a post distortion (PD) scheme, the non-linearity of one device is countered by another device. PD schemes are described in more detail, for example, in Namsoo Kim et al., “A Cellular-band CDMA 0.25 um CMOS LNA Linearized using Active Post-Distortion,” IEEE JSSC, Vol. 41, No. 7, July 2006, pp. 1532-1536. However, this scheme is also sensitive to frequency, making it undesirable for wideband applications as well. In an adaptive-biasing scheme, a transconductance (gm) stage uses a tail current that is changed based on the input voltage. This scheme is described in more detail, for example, in S. Sengupta, “Adaptively-biased Linear Transconductor,” IEEE CAS-I, Vol. 52, No. 11, November 2005, pp. 2369-2375. Conventional adaptively biased amplifiers are wideband in nature, but suffer from common-mode rejection ratio (CMRR) problems.
FIG. 1 illustrates an example conventional adaptively biased, differential pair amplifier circuit. As shown, amplifier 100 includes a gm stage 110, a current buffer stage 120, a tail current source stage 130, and an adaptive biasing circuit 160. The gm stage 110 includes two transistors 112 and 114 (e.g., JFETs), which are referred to as M1 and M2, respectively. An input voltage Vin may be applied differentially to the gates of M1 and M2. For example, in FIG. 1+Vin/2 is applied to the gate of M1, and −Vin/2 is applied to the gate of M2. The current buffer stage 120 includes cascade transistors 122 and 124 (e.g., JFETs), which are referred to as M3 and M4, respectively. Together, M3 and M4 make up a cascading pair. The tail current source stage 130 includes two tail current source transistors 132 and 134 (e.g., JFETs), which are referred to as M5 and M6, respectively. The adaptive biasing circuit 160 provides a DC biasing voltage to the gates of transistors M5 and M6, respectively. The adaptive biasing circuit 160 includes level shifters 162 and 164 that tap outputs of amplifier 100 (i.e., the connections between transistors M3 and M1, and the connections between transistors M4 and M2, respectively), and feed them back as a voltage reference Vsh to the tail current source stage 130 (i.e., to the gates of transistors M5 and M6, respectively). Level shifters 162 and 164 may be implemented using simple source followers, for example. Amplifier 100 also includes loads 102 and 104. Loads 102 and 104 therefore provide an impedance to convert the current in amplifier 100 to an output voltage, and may be implemented as resistors, inductors, etc.
Amplifier 100 is wired such that loads 102 and 104 are coupled to a common power supply voltage VDD at a first terminal, and to the drains of M3 and M4, respectively, at a second terminal. An output voltage Vout may be tapped from one of the second terminals of loads 102 and 104. For example, in FIG. 1, the connection between the second terminal of load 104 and the drain of M4 is tapped to provide +Vout, and the connection between the second terminal of load 102 and the drain of M3 is tapped to provide −Vout. The gates of M3 and M4 each receive the same biasing voltage VDD. The sources of M3 and M4 are connected to the drains of M1 and M2, respectively. The gates of M1 and M2 are connected differentially to the input voltage Vin as described above. The sources of M1 and M2 are tied together and connected to the drains of M5 and M6. As described above, the gates of M5 and M6 are connected to the feedback reference voltages Vsh provided by the level shifters 162 and 164. In this configuration, each of the six transistors M1 through M6 are matched and have their bulks connected to their sources.
Because M1 and M3 are matched and conduct equal amounts of current, their gate-to-source voltages (Vgs) are essentially equal. Similarly, the Vgs voltages of M2 and M4 are equal. Therefore, the voltage difference at the sources of M3 and M4 is equal to the differential input voltage Vin. These source voltages are fully-balanced even if the input signal is single ended due to the common-mode rejection of the differential pair M1 and M2. In this design, Vsh is adjusted such that the Vgs(M1)=Vgs(M3)=Vgs(M5). Thus, the balanced version of Vin is copied to the gate voltages of M5 and M6 by the level shifters 162 and 164, respectively.
It can be shown that the sum of the drain currents in M5 and M6 contain quadratic dependencies for nonlinearity cancellation. Furthermore, the DC operating current is determined by VDD and the feedback reference voltages Vsh, independent of the common-mode input level. In addition, fully-balanced signals are not required. The noise generated by the components in the squaring circuit may be reduced by the common-mode rejection of M1 and M2. The noise generated by the cascade transistors M3 and M4 may be relatively negligible due to the large impedance seen looking down from their source (resulting in a low effective gm). The high frequency performance may therefore be somewhat improved because the feedback signal does not have to propagate through several current mirrors.
However, the linearity of amplifier 100 still has notable deficiencies. For example, because the adaptive biasing circuit 160 taps the outputs, which have already undergone nonlinearity distortions in the various amplification stages, and then feeds them back to the tail current source stage 150, nonlinearities already present in the amplifier are further propagated by the adaptive biasing of amplifier 100. Furthermore, amplifier 100 uses DC coupling, which can affect the DC biasing conditions and hence gm linearization over changes in process, voltage, and temperature (PVT). The strong dependencies of the DC operating currents on VDD and Vsh also degrade the common-mode rejection ratio (CMRR).